In manufacturing thin body transistor with a thin channel, there are two issues that need to be addressed. One is dramatically increased series impedance caused by the thin channel layer. The other is over-etching issue in source/drain region during contact hole etching process.
The aforementioned two issues can be solved by introducing a raised source/drain structure or a recessed source/drain structure. However, there are limitations when applying the structures to a three-dimensional (3D) stackable device. Since the raised source/drain structure must be manufactured by a high temperature epitaxial process in greater than 800° C., the bottom transistor shall be damaged. In addition, although the recessed structure can be manufactured by low-temperature dry etching, the dry etching process tends to increase a surface roughness of the channel and interface defects caused by plasma bombardment, which deteriorates device characteristics. Therefore, the raised or recessed source/drain structure is not conducive to the development of 3D stackable device. In view of this, it is a main object of the invention to provide a high-performance 3D stackable device.